1. Field of the Disclosure
The subject disclosure relates to methods for forming electronic packages and the electronic packages themselves, and more particularly to an improved method for fabrication of 3D multi-die layer electronic packages.
2. Background of the Related Art
The need to increase packaging density in electronic products has led to the development of 3D packaging. Examples of 3D packaging include stacking die in a single package and interconnecting them using wirebonds or TSVs (through silicon vias or through substrate vias), or using solder to stack packaged devices (package-on-package). Stacked packages have also been connected by patterning the sides of the stack.
All of these methods have significant limitations. Wirebonding places significant geometric restrictions on the die and the physical layout. Soldering limits the number of possible connections. Connecting packages along the edge of the stack introduces significant routing constraints.